Parallel plate slot antenna. Platform Embedded Slot Antenna Backed by Shielded Parallel Plate Resonator

Otherwise, you should try different models with different fictitious boundaries, and analyze the resulting error distributions and fields. Maybe, you already have enough experience with fictitious boundaries from the scattering and grating models, for setting it at a good position.

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In blockanother e. It should be understood that a greater number or fewer metal layers and different configurations thereof may be employed within the scope of the present principles. In blockfabricating vias is performed. The plated-through holes vias V3 g, V3 p, V3 s are fabricated afterward.

Feed area To obtain the simplest solution, assume that you have the fundamental mode in the parallel plate waveguide.

A system includes a radio frequency integrated circuit RFIC. The vertical transition is surrounded by ground vias The aperture-coupled patch antenna is implemented on a top section of the package Technical Field The present invention relates to antenna and feed line designs for radio frequency integrated circuit RFIC chip packages, and, more particularly, to chip packaging with integrated antennas or planar phased array designs with high performance antennas and their feed lines for millimeter-wave frequencies and above.

The parallel-plate mode suppression mechanism includes a grounded reflector that forms a cage with the grounded vias around an antenna region and further includes second ground vias surrounding the signal via. The package production cost is lowered since no internal cavity is used. Therefore, you should have no major problems with the slot antenna.

By placing a cage using reflector and vias V2 below the apertureparallel-plate modes will be reduced.

Measurements verify the proposed antenna exhibits excellent gain and front-to-back ratio FTBR. Is the reflection coefficient of the fundamental mode in the feed area close to zero?

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In one embodiment, printed circuit board PCB technology is employed. A plurality of antennas may be employed in a phased array.

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For this reason, you can introduce a second fictitious boundary that separates the slot area from free space. The substrates may include prepregnated boards epoxy resin boards or other substrate boards or materials.

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The antenna may include single or differential feed lines. A package interface to the chip and a printed circuit board PCB not shown is implemented at a bottom section of the package In this embodiment, the array includes a single RFIC chip with four feed lines to dayz server slots antenna The package structure has a first portion and a second portion on opposing sides, the first portion including at least one antenna and ground plane integrated in the package structure, the second portion including pads to bond with the RFIC and at least one conductive plane parallel to the ground plane.

The packages with integrated antennas are based on multilayer printed circuit board PCB or low temperature cofired ceramic LTCC technologies. One advantage of the architecture is that all antenna elements can be implemented in a planar way and an RFIC module can be packaged with the antenna elements simultaneously.

A lamination process may be employed to form L1 p.

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When the fictitious boundary is sufficiently far away from the slot, the field of these modes is so small that it can be neglected. The patch is formed on metal layer M0. The chip package as recited in claim 1wherein the first grounded vias include a spacing of less than 0.

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This fictitious boundary can be more or less close to the slot, somewhere in the parallel plate waveguide. Since the PEC wall is infinite, you can only model part of it.

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Referring toplanar views of package structures using slot loop antennas with single-ended FIG. Fictitious boundaries To define special expansions for the feed region of the antenna, separate this region and the slot antenna itself by a fictitious boundary.

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Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.

To reduce a number of via depth types, via V1 may stop at the antenna ground plane level M1instead of at the feed line level M2but with an antipad so that the via V1 does not touch the ground plane. Remember that you have already studied parallel plate waveguides and slots in the scattering section.

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Differential signal vias carry the signals to differential feed lines which interact with a patch and slots to propagate the differential signal. The chip package as recited in claim 1wherein the antenna includes one of a slot or a slot loop antenna.

The packaging technology in accordance with the present principles is consistent with PCB and LTCC manufacturing processes and can be used for packages with an integrated antenna or antenna array. The package has at least two ground planes, one ground plane for the antenna in metal layer M1 and another ground plane in metal layer Parallel plate slot antenna for the reflector The antenna may include a regular patch antenna, a stacked patch antenna, a cavity-backed aperture-coupled patch antenna, a slot antenna, a slot loop antenna, etc.

The pads are preferably external to the package and permit the integrated circuit e. This forms L1 b. When the fictitious boundary is near the slot, the field in the feed region is relatively complicated and must be modeled with higher order modes that are evanescent.

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